This invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming trench isolation between elements in a semiconductor device without humps in subthreshold current regions.
Many non LOCOS isolation techniques have been reported to realize submicron isolation in a semiconductor device (T. Shibata et al., IEDM Tech. Dig., pp. 27-30, Dec. 1983; K. Terada et al., IEEE Trans. on Electron Devices, Vol. ED-31, pp. 1308-1313, Sept. 1981). Above all, the trench isolation technique with buried oxide is thought of as a leading technique. However, n-MOS FETs fabricated with the trench isolation frequently show humps in subthreshold current regions and a reverse narrow width effect in threshold voltages (T. Iizuka et al., IEDM Tech. Dig., pp. 380-383, Dec. 1981). In order to eliminate these disadvantages, increasing boron concentration at side-walls of channel edges seems to be effective. For implanting boron ions into the side-walls, tapered etching of the isolation side-walls in a silicon substrate was proposed (Kurosawa et al., IEDM Tech. Dig., pp. 384 Dec. 1981). That is, V-letter-shaped isolation is used to increase boron concentration at side-walls thereof. However, the minimum isolation width W.sub.I may be limited by 2D tan .alpha., where D and .alpha. are isolation depth and taper angle, respectively. For example, W.sub.I is limited to be about 0.69 .mu.m for D=0.6 .mu.m and .alpha.=60.degree..